ASIC and FPGA verification a guide to component modeling

Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate v...

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Bibliographic Details
Main Author Munden, Richard
Format Electronic eBook
LanguageEnglish
Published San Francisco, Calif. : Morgan Kaufmann, ©2005.
SeriesMorgan Kaufmann series in systems on silicon.
Subjects
Application-specific integrated circuits.
elektronické knihy
electronic books
Online AccessFull text
ISBN9781417549719
9780125105811
9780080475929
Physical Description1 online zdroj (1 volume).

Cover

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505 0 |a 1. Introduction to Board-Level Verification; 2. Tour of a simple model; 3. VHDL packages for component models; 4. Introduction to SDF; 5. Anatomy of a VITAL Model; 6. Modeling Delays; 7. VITAL truth tables; 8. Modeling timing constraints; 9. Modeling registered devices; 10. Conditional delays and timing constraints; 11. Negative timing constraints; 12. Timing Files and Backannotation; 13. Adding Timing to Your RTL Code; 14. Modeling Memories; 15. Considerations for Component Modeling; 16. Modeling Component Centric Features; 17. Testbenches for Component Models. 
520 |a Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of todays digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. *Provides numerous models and a clearly defined methodology for performing board-level simulation. *Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification. 
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