ASIC and FPGA verification a guide to component modeling

Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate v...

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Bibliographic Details
Main Author: Munden, Richard.
Format: eBook
Language: English
Published: San Francisco, Calif. : Morgan Kaufmann, ©2005.
Series: Morgan Kaufmann series in systems on silicon.
Subjects:
Application-specific integrated circuits.
elektronické knihy
electronic books
ISBN: 9781417549719
9780125105811
9780080475929
Physical Description: 1 online zdroj (1 volume).

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Table of contents

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006 m o d
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008 041028s2005 cau fs 001 0 eng d
020 |a 9781417549719  |q (ebook) 
020 |a 9780125105811 
020 |a 9780080475929  |q (ebook) 
035 |a (OCoLC)56837419  |z (OCoLC)162575769  |z (OCoLC)880334328 
040 |a N$T  |b eng  |e pn  |c N$T  |d OCLCQ  |d YDXCP  |d OCLCQ  |d OCLCO  |d OCLCQ  |d OCLCF  |d NLGGC  |d OCLCQ  |d OPELS  |d SLY 
100 1 |a Munden, Richard. 
245 1 0 |a ASIC and FPGA verification  |h [elektronický zdroj] :  |b a guide to component modeling /  |c Richard Munden. 
260 |a San Francisco, Calif. :  |b Morgan Kaufmann,  |c ©2005. 
300 |a 1 online zdroj (1 volume). 
336 |a text  |b txt  |2 rdacontent 
337 |a počítač  |b c  |2 rdamedia 
338 |a online zdroj  |b cr  |2 rdacarrier 
490 1 |a Morgan Kaufmann series in systems on silicon 
500 |a Includes index. 
505 0 |a 1. Introduction to Board-Level Verification; 2. Tour of a simple model; 3. VHDL packages for component models; 4. Introduction to SDF; 5. Anatomy of a VITAL Model; 6. Modeling Delays; 7. VITAL truth tables; 8. Modeling timing constraints; 9. Modeling registered devices; 10. Conditional delays and timing constraints; 11. Negative timing constraints; 12. Timing Files and Backannotation; 13. Adding Timing to Your RTL Code; 14. Modeling Memories; 15. Considerations for Component Modeling; 16. Modeling Component Centric Features; 17. Testbenches for Component Models. 
520 |a Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of todays digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. *Provides numerous models and a clearly defined methodology for performing board-level simulation. *Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification. 
590 |a Knovel Library  |b ACADEMIC - Computer Hardware Engineering 
506 |a Plný text je dostupný pouze z IP adres počítačů Univerzity Tomáše Bati ve Zlíně nebo vzdáleným přístupem pro zaměstnance a studenty univerzity 
650 0 |a Application-specific integrated circuits. 
655 7 |a elektronické knihy  |7 fd186907  |2 czenas 
655 9 |a electronic books  |2 eczenas 
776 0 8 |i Print version:  |a Munden, Richard.  |t ASIC and FPGA verification.  |d San Francisco, Calif. : Morgan Kaufmann, ©2005  |z 0125105819  |w (OCoLC)56642597 
830 0 |a Morgan Kaufmann series in systems on silicon. 
856 4 0 |u https://proxy.k.utb.cz/login?url=http://app.knovel.com/hotlink/toc/id:kpASICFPG4/asic_and_fpga_verification__a_guide_to_component_modeling  |y Plný text 
992 |a BK  |c KNOVEL 
999 |c 78159  |d 78159 

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