ASIC and FPGA verification a guide to component modeling

• Main Author: Munden, Richard
• Format: Electronic eBook
• Language: English
• Published: San Francisco, Calif. : Morgan Kaufmann, ©2005.
• Series: Morgan Kaufmann series in systems on silicon.
• Subjects: Application-specific integrated circuits.; elektronické knihy; electronic books
• ISBN: 9781417549719; 9780125105811; 9780080475929
• Physical Description: 1 online zdroj (1 volume).
• Item Description: Includes index.
• Access: Plný text je dostupný pouze z IP adres počítačů Univerzity Tomáše Bati ve Zlíně nebo vzdáleným přístupem pro zaměstnance a studenty univerzity

Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of todays digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. *Provides numerous models and a clearly defined methodology for performing board-level simulation. *Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification.