ASIC and FPGA verification a guide to component modeling

Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate v...

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Bibliographic Details
Main Author Munden, Richard
Format Electronic eBook
LanguageEnglish
Published San Francisco, Calif. : Morgan Kaufmann, ©2005.
SeriesMorgan Kaufmann series in systems on silicon.
Subjects
Online AccessFull text
ISBN9781417549719
9780125105811
9780080475929
Physical Description1 online zdroj (1 volume).

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