Secured Hardware Accelerators for DSP and Image Processing Applications
This book presents state-of-the art security solutions and optimization algorithms employed for designing secured hardware accelerators for DSP, multimedia and image processing applications. Broadly, the theme of this book includes the following: secured and optimized hardware accelerators for DSP a...
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| Main Author | |
|---|---|
| Format | Electronic eBook |
| Language | English |
| Published |
Stevenage
The Institution of Engineering and Technology
2020
|
| Series | Materials, circuits and devices series ;
76. |
| Subjects | |
| Online Access | Full text |
| ISBN | 1839533072 9781839533075 9781839533068 1839533064 |
| Physical Description | 1 online resource (xl, 364 pages) illustrations |
Cover
| LEADER | 00000cam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | kn-on1227392889 | ||
| 003 | OCoLC | ||
| 005 | 20240717213016.0 | ||
| 006 | m o d | ||
| 007 | cr cn||||||||| | ||
| 008 | 201219t20202021enka ob 001 0 eng d | ||
| 040 | |a EBLCP |b eng |e rda |e pn |c EBLCP |d UKAHL |d RB# |d OCLCF |d CUS |d OCLCO |d STF |d UIU |d CUV |d N$T |d OCLCO |d OCLCQ |d OCLCO |d OCLCL |d TMA |d OCLCQ | ||
| 020 | |a 1839533072 |q electronic bk. | ||
| 020 | |a 9781839533075 |q (electronic bk.) | ||
| 020 | |z 9781839533068 | ||
| 020 | |z 1839533064 | ||
| 024 | 7 | |a 10.1049/PBCS076E |2 doi | |
| 035 | |a (OCoLC)1227392889 |z (OCoLC)1243109416 | ||
| 100 | 1 | |a Sengupta, Anirban |c (Computer scientist), |e author. |1 https://id.oclc.org/worldcat/entity/E39PCjqWHxv7H8Gqj9wfPCM96q | |
| 245 | 1 | 0 | |a Secured Hardware Accelerators for DSP and Image Processing Applications |c Anirban Sengupta |
| 264 | 1 | |a Stevenage |b The Institution of Engineering and Technology |c 2020 | |
| 264 | 4 | |c ©2021 | |
| 300 | |a 1 online resource (xl, 364 pages) |b illustrations | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 490 | 1 | |a IET materials, circuits and devices series |v 76 | |
| 504 | |a Includes bibliographical references and index | ||
| 505 | 0 | |a Introduction : secured and optimized hardware accelerators for DSP and image processing applications / Anirban Sengupta -- Cryptography-driven IP steganography for DSP hardware accelerators / Anirban Sengupta -- Double line of defence to secure JPEG codec hardware for medical imaging systems / Anirban Sengupta -- Integrating multi-key-based structural obfuscation and low-level watermarking for double line of defence of DSP hardware accelerators / Anirban Sengupta -- Multimodal hardware accelerators for image processing filters / Anirban Sengupta -- Fingerprint biometric for securing hardware accelerators / Anirban Sengupta -- Key-triggered hash-chaining-based encoded hardware steganography for securing DSP hardware accelerators / Anirban Sengupta -- Designing a secured N-point DFT hardware accelerator using obfuscation and steganography / Anirban Sengupta and Mahendra Rathor -- Structural transformation-based obfuscation using pseudo-operation mixing for securing data-intensive IP cores / Anirban Sengupta and Mahendra Rathor | |
| 500 | |a Written by an acknowledged expert in the field, this book focuses on approaches for designing secure hardware accelerators for digital signal processing and image processing. State-of-the art security and optimization algorithms are presented, and their roles in the design of secured hardware accelerators explored | ||
| 506 | |a Plný text je dostupný pouze z IP adres počítačů Univerzity Tomáše Bati ve Zlíně nebo vzdáleným přístupem pro zaměstnance a studenty | ||
| 520 | |a This book presents state-of-the art security solutions and optimization algorithms employed for designing secured hardware accelerators for DSP, multimedia and image processing applications. Broadly, the theme of this book includes the following: secured and optimized hardware accelerators for DSP and image processing applications; cryptography-driven IP steganography for DSP hardware accelerators; double line of defence to secure JPEG codec hardware for medical imaging systems; integrating multi-key-based structural obfuscation and low-level watermarking for double line of defence of DSP hardware accelerators; multimodal hardware accelerators for image processing filters; fingerprint biometric for securing hardware accelerators; key-triggered hash-chaining-based encoded hardware steganography for securing DSP hardware accelerators; N-point DFT hardware accelerator design using obfuscation and steganography; and structural transformation and obfuscation frameworks for data-intensive IPs. | ||
| 590 | |a Knovel |b Knovel (All titles) | ||
| 650 | 0 | |a Image processing. | |
| 650 | 0 | |a Imaging systems in medicine. | |
| 650 | 0 | |a Particle accelerators. | |
| 650 | 0 | |a Cryptography. | |
| 650 | 0 | |a Public key cryptography. | |
| 655 | 7 | |a elektronické knihy |7 fd186907 |2 czenas | |
| 655 | 9 | |a electronic books |2 eczenas | |
| 776 | 0 | 8 | |i Print version: |a Sengupta, Anirban |t Secured Hardware Accelerators for DSP and Image Processing Applications |d Stevenage : Institution of Engineering & Technology,c2021 |z 9781839533068 |
| 830 | 0 | |a Materials, circuits and devices series ; |v 76. | |
| 856 | 4 | 0 | |u https://proxy.k.utb.cz/login?url=https://app.knovel.com/hotlink/toc/id:kpSHADSPI2/secured-hardware-accelerators?kpromoter=marc |y Full text |