Secured Hardware Accelerators for DSP and Image Processing Applications

This book presents state-of-the art security solutions and optimization algorithms employed for designing secured hardware accelerators for DSP, multimedia and image processing applications. Broadly, the theme of this book includes the following: secured and optimized hardware accelerators for DSP a...

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Bibliographic Details
Main Author: Sengupta, Anirban (Computer scientist), (Author)
Format: eBook
Language: English
Published: Stevenage The Institution of Engineering and Technology 2020
Series: Materials, circuits and devices series ; 76.
Subjects:
ISBN: 1839533072
9781839533075
9781839533068
1839533064
Physical Description: 1 online resource (xl, 364 pages) illustrations

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Summary: This book presents state-of-the art security solutions and optimization algorithms employed for designing secured hardware accelerators for DSP, multimedia and image processing applications. Broadly, the theme of this book includes the following: secured and optimized hardware accelerators for DSP and image processing applications; cryptography-driven IP steganography for DSP hardware accelerators; double line of defence to secure JPEG codec hardware for medical imaging systems; integrating multi-key-based structural obfuscation and low-level watermarking for double line of defence of DSP hardware accelerators; multimodal hardware accelerators for image processing filters; fingerprint biometric for securing hardware accelerators; key-triggered hash-chaining-based encoded hardware steganography for securing DSP hardware accelerators; N-point DFT hardware accelerator design using obfuscation and steganography; and structural transformation and obfuscation frameworks for data-intensive IPs.
Item Description: Written by an acknowledged expert in the field, this book focuses on approaches for designing secure hardware accelerators for digital signal processing and image processing. State-of-the art security and optimization algorithms are presented, and their roles in the design of secured hardware accelerators explored
Bibliography: Includes bibliographical references and index
ISBN: 1839533072
9781839533075
9781839533068
1839533064
Access: Plný text je dostupný pouze z IP adres počítačů Univerzity Tomáše Bati ve Zlíně nebo vzdáleným přístupem pro zaměstnance a studenty