ASIC and FPGA verification : a guide to component modeling

Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate v...

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Bibliographic Details
Main Author Munden, Richard
Format Electronic eBook
LanguageEnglish
Published Amsterdam ; Boston : Elsevier, ©2005.
SeriesMorgan Kaufmann series in systems on silicon.
Subjects
Online AccessFull text
ISBN9780125105811
0125105819
0080475922
9780080475929
1592782485
9781592782482
Physical Description1 online resource (xx, 316 pages) : illustrations

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