Method for fabricating a semiconductor device using a modeling algorithm to model the proximity effect from the sub-layer
A method for forming a circuit layout comprises performing process proximity effect modeling based on process proximity effects caused by a sub-layer, wherein the sub-layer comprises an active layer positioned under a gate poly, and wherein performing the process proximity effect modeling includes c...
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| Format | Patent |
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| Language | English |
| Published |
08.10.2013
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| Online Access | Get full text |
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| Summary: | A method for forming a circuit layout comprises performing process proximity effect modeling based on process proximity effects caused by a sub-layer, wherein the sub-layer comprises an active layer positioned under a gate poly, and wherein performing the process proximity effect modeling includes calculating a pattern density of the sub-layer, incorporating results of the process proximity effect modeling into a modeling algorithm, and performing proximity correction using the results to manipulate a layout of a mask to be used when forming the circuit layout by photolithography. |
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