Optimizing Test Scheduling for System-on-a-Chip (SOC) Design Using Neural Network Approach

This paper presents the modeling and solution approach for the new System-on-a-Chip (SOC) design test scheduling problems. To solve the SOC design test problems, a neural network (NN) combined with heuristic algorithm has been developed. The SOC design test scheduling and optimization are subject to...

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Bibliographic Details
Published inIISE Annual Conference. Proceedings p. 1
Main Authors Kloypayan, Jirawan, Lee, Yuan-Shin
Format Journal Article
LanguageEnglish
Published Norcross Institute of Industrial and Systems Engineers (IISE) 01.01.2002
Subjects
Electronics industry
Industrial engineering
Neural networks
Optimization
Scheduling
Semiconductors
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Summary:This paper presents the modeling and solution approach for the new System-on-a-Chip (SOC) design test scheduling problems. To solve the SOC design test problems, a neural network (NN) combined with heuristic algorithm has been developed. The SOC design test scheduling and optimization are subject to four different constraints: (i) precedence constraint, (ii) resource constraint, (iii) core constraint, and (iv) power constraint. Computer implementation and practical testing examples are presented in this paper. The results demonstrate that the developed model with the soft computing techniques can successfully solve a large size SOC test scheduling problem within a reasonable time. The techniques presented in this paper can be used for the optimization of the SOC design testing that is important for current development in the semiconductor and electronics industry. [PUBLICATION ABSTRACT]
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