Reliability of Nano-Scaled Logic Gates Based on Binary Decision Diagrams

• Published in: Proceedings of the International Conference on Modeling, Simulation and Visualization Methods (MSV) p. 1
• Main Authors: Beg, Azam, Beg, Ajmal
• Format: Conference Proceeding
• Language: English
• Published: Athens The Steering Committee of The World Congress in Computer Science, Computer Engineering and Applied Computing (WorldComp) 01.01.2014

Binary decision diagrams (BDDs) have been useful for synthesis and verification of digital circuits. This paper, for the first time, looks into the reliability of a few logic gates implemented using BDDs. The gates were designed using an advanced CMOS technology node and subject to threshold-voltage variations. The results of the Monte Carlo Spice simulations show that BDD-based gates are significantly more reliable than their conventional CMOS counterparts.