A 10.3125 Gb/s Deserializer for IEEE 10G-EPON Standard

• Published in: IDEC Journal of Integrated Circuits and Systems, 5(2) pp. 1 - 8
• Main Authors: 황원준, 최윤식, 정보윤, 백광현
• Format: Journal Article
• Language: English
• Published: 반도체설계교육센터 01.04.2019
• Subjects: 전기공학
• ISSN: 2384-2113
• DOI: 10.23075/jicas.2019.5.2.001

The throughput requirement of high-speed interface such as wireline I/O and memory I/O has been increased even if the power budget for the interface circuits has been maintained and decreased. This paper, true single-phase clock logic and half-rate architecture to implement the 16-to-1 10.3125 GB/s deserializer is used to minimize the power consumption with remaining high-speed operation. The design method for essential block such as demultiplexer, clock data recovery circuit, continuous time linear equalizer, decision feedback equalizer and lock detector is also described in paper. The designed deserializer is fabricated through 65nm CMOS process and dissipate about 200mW is satisfied with IEEE standard. The developed deserializer has BER 10-12 with PRBS 2 9 -1. KCI Citation Count: 0