New Code Generation Algorithm for QueueCore An Embedded Processor with High ILP

• Published in: Eighth International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2007) pp. 185 - 192
• Main Authors: Canedo, A., Abderazek, B.A., Sowa, M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2007
• Subjects: Computational modeling; Distributed computing; Encoding; Hardware; Parallel processing; Processor scheduling; Program processors; Reduced instruction set computing; Registers; Scheduling algorithm
• ISBN: 0769530494; 9780769530499
• ISSN: 2379-5352
• DOI: 10.1109/PDCAT.2007.12

Modern architectures rely on exploiting parallelism found at the instruction level to achieve high performance. Aggressive ILP compilers expose high amounts of instruction level parallelism where, in some cases, the number of architected registers is not enough to hold the results of potential parallel instructions. This paper presents a new code generation scheme for the QueueCore, a 32-bit queue-based architecture capable of executing high amounts of ILP. QueueCore's instructions implicitly read their operands and write results. Compiling for the QueueCore requires that all instructions have at most one explicit operand represented as an offset calculated at compile-time. Additionally, the instructions must be scheduled in level-order manner. The proposed algorithm successfully restricts all instructions to have at most one offset reference, it computes the offset values, and makes a level-order scheduling of the program. To evaluate the effectiveness of the new code generation scheme we developed a queue compiler and compiled a set of benchmark programs. Our results show that the code has more parallelism than optimized RISC code by factors ranging from 1.12 to 2.30. QueueCore's instruction set allows us to generate code about 40%-18% denser than optimized RISC code.