Area, performance, and sensitizable paths /spl lsqb/logic design/spl rsqb

In this paper, we investigate the problem of modifying a synthesized circuit to improve its path sensitizability. It is shown that a large number of paths, which cannot be sensitized using single-transition tests, are redundant paths and they can be removed by appropriate modification of the circuit...

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Bibliographic Details
Published inGreat Lakes 4th Symposium on VLSI: Design Automation of High Performance VLSI Systems pp. 222 - 227
Main Authors Kapoor, B., Nair, V.S.S.
Format Conference Proceeding
LanguageEnglish
Published IEEE Comput. Soc. Press 1994
Subjects
Benchmark testing
Circuit faults
Circuit synthesis
Circuit testing
Combinational circuits
Computer science
Delay
Logic design
Robustness
Terminology
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ISBN0818656107
9780818656101
DOI10.1109/GLSV.1994.289965

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Summary:In this paper, we investigate the problem of modifying a synthesized circuit to improve its path sensitizability. It is shown that a large number of paths, which cannot be sensitized using single-transition tests, are redundant paths and they can be removed by appropriate modification of the circuit. The effect of these modifications on area and performance of the circuit has been analyzed. For the paths which are neither redundant nor sensitizable using single-transition tests, it is shown that they can be sensitized using multiple-transition tests. Results obtained on some common benchmark examples suggest the validity and viability of this approach.< >
ISBN:0818656107
9780818656101
DOI:10.1109/GLSV.1994.289965