Micro-architecturally delayed timer

Techniques are described for injecting noise in a timer value provided to an instruction requesting the timer value. A plurality of tasks may execute on a processor, wherein the processor may comprise one or more processing cores and each task may include a plurality of computer executable instructi...

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Bibliographic Details
Main Authors Patel Rahul Gautam, Earl William John, Potlapally Nachiketh Rao
Format Patent
LanguageEnglish
Published 05.09.2017
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Techniques are described for injecting noise in a timer value provided to an instruction requesting the timer value. A plurality of tasks may execute on a processor, wherein the processor may comprise one or more processing cores and each task may include a plurality of computer executable instructions. In accordance with one technique for injecting noise in the timer value, in response to a request for a timer value, an artificial and indeterminate amount of delay may be introduced before accessing of the timer value from the hardware timer. In one implementation, access to the hardware timer for the timer value may be gated by one or more artificially injected micro-architectural events.
Bibliography:Application Number: US201414509980