Storage circuit with random number generation mode

A storage circuit 2 in the form of a master slave latch includes a slave stage 6 serving as a bit storage circuit. The slave stage 6 includes an inverter chain which when operating in a normal mode includes an even number of inverters 10, 12 and when operating in an random number generation mode inc...

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Bibliographic Details
Main Authors IDGUNJI SACHIN SATISH, CHANDRA VIKAS
Format Patent
LanguageEnglish
Published 22.09.2015
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A storage circuit 2 in the form of a master slave latch includes a slave stage 6 serving as a bit storage circuit. The slave stage 6 includes an inverter chain which when operating in a normal mode includes an even number of inverters 10, 12 and when operating in an random number generation mode includes an odd number of inverters 10, 12, 14 and so functions as a free running ring oscillator. When a switch is made back from the random number generation mode to the normal mode, then the oscillation ceases and a stable pseudo random bit value is output from the bit value storage circuit 6.
Bibliography:Application Number: US201213678621