Flash memory system and designing method of flash translation layer thereof

The method of designing a flash translation layer includes receiving a logical address according to an external request and mapping a physical address that corresponds to the logical address. The mapping manages continuous logical addresses and physical addresses corresponding to the logical address...

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Bibliographic Details
Main Authors PARK CHANIK, LEE YONG-GOO, KIM JIN SOO, KANG JEONGUK
Format Patent
LanguageEnglish
Published 23.07.2013
Subjects
CALCULATING
CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION ANDCOMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION ANDCOMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWNENERGY USE
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS
PHYSICS
TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE
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Summary:The method of designing a flash translation layer includes receiving a logical address according to an external request and mapping a physical address that corresponds to the logical address. The mapping manages continuous logical addresses and physical addresses corresponding to the logical addresses as one mapping unit.
Bibliography:Application Number: US20090588198