Global planarization of wafer scale package with precision die thickness control

• Main Authors: CHEN HOWARD HAO, HSU LOUIS L, JI BRIAN L
• Format: Patent
• Language: English
• Published: 28.02.2006
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; SEMICONDUCTOR DEVICES; TECHNICAL SUBJECTS COVERED BY FORMER USPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS

In accordance with the present invention, a method for producing at least two different chips with a controlled total chip thickness such that when these chips are placed into a corresponding pocket of a plurality of pockets located in a wafer chip carrier wherein each of the plurality of pockets have a total pocket depth (Tdp) at least substantially equal to one another, a substantially planarized top surface of said wafer chip carrier is achieved. The method comprises forming at least a first chip on a first dummy carrier and at least a second chip different from the first chip on a separate second dummy carrier using partial wafer bonding and partial wafer dicing. The method further includes using a chip thickness control mechanism in conjunction with said partial wafer bonding and partial wafer dicing in forming the at least a first chip and at least second chip different from the first chip, such that the at least first chip and the at least second different chip formed from each carrier each have a final total chip thickness (FTC) which is substantially equal to one another, and an FTC which is substantially equal to a total pocket depth (Tdp) of each of the uniform pockets of said wafer chip carrier, minus the final thickness of an attaching material (FTG) used within said each respective pocket.