Method and apparatus for reducing the number of programmable architecture elements required for implementing a look-up table in a programmable logic device
A method and apparatus for reducing the number of programmable architecture elements required for implementing a look-up table in a programmable logic device. At least one logic function to be performed by the look-up table is chosen. An output state is determined for each set of inputs to the look-...
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Main Authors | , , |
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Format | Patent |
Language | English |
Published |
14.09.1999
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Edition | 6 |
Subjects | |
Online Access | Get full text |
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Summary: | A method and apparatus for reducing the number of programmable architecture elements required for implementing a look-up table in a programmable logic device. At least one logic function to be performed by the look-up table is chosen. An output state is determined for each set of inputs to the look-up table, the output state being an array of outputs of the look-up table. Each output state is made up of responses of the chosen logic functions to a particular set of input variables. Identical output states are formed into groups. Selected groups of the output states which do not require programmable architecture elements are eliminated. A programmable architecture element is then assigned for each remaining group of output states. |
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Bibliography: | Application Number: US19940259360 |