Circuit arrangement, network-on-chip and method for transmitting information
A circuit arrangement, network-on-chip, and a method for transmitting information are disclosed. In one embodiment, an electrical circuit is provided comprising a plurality of circuit blocks comprising a first circuit block, a second circuit block, and a third circuit block, and a connection structu...
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| Main Authors | , |
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| Format | Patent |
| Language | English |
| Published |
13.11.2018
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| Subjects | |
| Online Access | Get full text |
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| Summary: | A circuit arrangement, network-on-chip, and a method for transmitting information are disclosed. In one embodiment, an electrical circuit is provided comprising a plurality of circuit blocks comprising a first circuit block, a second circuit block, and a third circuit block, and a connection structure coupled to the plurality of circuit blocks, wherein the first circuit block is configured to send a request comprising information corresponding to the request and an address onto the connection structure, wherein the second circuit block is configured to initiate a transmission onto the connection structure in response to receiving the request, and wherein the third circuit block is configured to receive the transmission and wherein the address is assigned to the third circuit block. |
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| Bibliography: | Application Number: US20100874250 |