PIXEL ARRAY AREA OPTIMIZATION USING STACKING SCHEME FOR HYBRID IMAGE SENSOR WITH MINIMAL VERTICAL INTERCONNECTS

Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size...

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Bibliographic Details
Main Author BLANQUART LAURENT
Format Patent
LanguageEnglish
Korean
Published 05.03.2014
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PICTORIAL COMMUNICATION, e.g. TELEVISION
SEMICONDUCTOR DEVICES
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Summary:Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed. Embodiments of the above may include systems, methods and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor using vertical interconnects are also disclosed.
Bibliography:Application Number: KR20137031083