Using type bits to track storage of ecc and predecode bits in a level two cache

• Main Author: ZURASKI GERALD D. JR
• Format: Patent
• Language: Chinese; English
• Published: 18.08.2004
• Edition: 7
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

本发明揭示了一种微处理器，该微处理器被设定成储存被舍弃的指令及数据字节。在一个实施例中，该微处理器包含预解码单元、指令高速缓存、数据高速缓存、及二级高速缓存。该预解码单元接收指令字节，并生成对应的预解码信息，且该预解码信息连同所述指令字节被储存在该指令高速缓存。该数据高速缓存接收并储存数据字节。该二级高速缓存被设定成：接收并储存来自该指令高速缓存的被舍弃的指令字节、以及奇偶校验信息及预解码信息，且接收并储存来自该数据高速缓存的被舍弃的数据字节、以及错误校正码位。可将指示位储存在缓存行部分，以便指示该缓存行中储存的数据的类型。 A microprocessor configured to store victimized instruction and data bytes is disclosed. In one embodiment, the microprocessor includes a predecode unit, and instruction cache, a data cache, and a level two cache. The predecode unit receives instruction bytes and generates corresponding predecode information that is stored in the instruction cache with the instruction bytes. The data cache receives and stores data bytes. The level two cache is configured to receive and store victimized instruction bytes from the instruction cache along with parity information and predecode information, and victimized data bytes from the data cache along with error correction code bits. Indicator bits may be stored on a cache line basis to indicate the type of data is stored therein.