Serializer and deserializer for odd ratio parallel data bus

• Main Authors: LEE CHULKYU, SU WENJUN, ZHANG LE
• Format: Patent
• Language: Chinese; English
• Published: 22.02.2017
• Subjects: BASIC ELECTRONIC CIRCUITRY; CALCULATING; CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION ANDCOMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION ANDCOMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWNENERGY USE; CODE CONVERSION IN GENERAL; CODING; COMPUTING; COUNTING; DECODING; ELECTRIC DIGITAL DATA PROCESSING; ELECTRICITY; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; INFORMATION STORAGE; PHYSICS; STATIC STORES; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS; TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE

Serializers and deserializers for odd ratio parallel data buses are disclosed. In one embodiment, serializers and deserializers operating with an odd number of parallel data bits work with a half-rate clock to provide a serial data stream at a full clock rate. By providing a half-rate clock, power and area are conserved on the integrated circuit incorporating the serializer. Additionally, by providing a 7:1 serializer, the bus is now compatible with the MIPI C-PHY standard. 公开了用于奇数比并行数据总线的串行化器和解串器。在个实施例中，以奇数个并行数据比特操作的串行化器和解串器在半速率时钟下工作来以全时钟速率提供串行数据流。通过提供半速率时钟，在纳入该串行化器的集成电路上节省了功率和面积。另外，通过提供7:1串行化器，总线现在与MIPI C-PHY标准兼容。