A 75-Gb/s/mm 2 and Energy-Efficient LDPC Decoder Based on a Reduced Complexity Second Minimum Approximation Min-Sum Algorithm

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Bibliographic Details
Published inIEEE transactions on very large scale integration (VLSI) systems Vol. 28; no. 4; pp. 926 - 939
Main Authors Lopez, Henry, Chan, Hsun-Wei, Chiu, Kang-Lun, Tsai, Pei-Yun, Jou, Shyh-Jye Jerry
Format Journal Article
LanguageEnglish
Published 01.04.2020
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ISSN1063-8210
1557-9999
DOI10.1109/TVLSI.2019.2955925

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ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2019.2955925