GPU-friendly floating random walk algorithm for capacitance extraction of VLSI interconnects

• Published in: Proceedings of the Conference on Design, Automation and Test in Europe pp. 1661 - 1666
• Main Authors: Zhai, Kuangya, Yu, Wenjian, Zhuang, Hao
• Format: Conference Proceeding
• Language: English
• Published: San Jose, CA, USA EDA Consortium 18.03.2013
• Series: ACM Conferences
• Subjects: Hardware > Hardware validation; Hardware > Integrated circuits > Interconnect; Hardware > Very large scale integration design
• ISBN: 9781450321532; 1450321534
• DOI: 10.5555/2485288.2485682

The floating random walk (FRW) algorithm is an important field-solver algorithm for capacitance extraction, which has several merits compared with other boundary element method (BEM) based algorithms. In this paper, the FRW algorithm is accelerated with the modern graphics processing units (GPUs). We propose an iterative GPU-based FRW algorithm flow and the technique using an inverse cumulative probability array (ICPA), to reduce the divergence among walks and the global-memory accessing. A variant FRW scheme is proposed to utilize the benefit of ICPA, so that it accelerates the extraction of multi-dielectric structures. The technique for extracting multiple nets concurrently is also discussed. Numerical results show that our GPU-based FRW brings over 20X speedup for various test cases with 0.5% convergence criterion over the CPU counterpart. For the extraction of multiple nets, our GPU-based FRW outperforms the CPU counterpart by up to 59X.