Altera Max Plus II Development Environment in Fault Simulation and Test Implementation of Embedded Cores-Based Sequential Circuits

• Published in: Distributed Computing - IWDC 2004 pp. 353 - 360
• Main Authors: Das, Sunil R., Jin, Chuan, Jin, Liwu, Assaf, Mansour H., Petriu, Emil M., Sahinoglu, Mehmet
• Format: Book Chapter
• Language: English
• Published: Berlin, Heidelberg Springer Berlin Heidelberg 01.01.2004
• Series: Lecture Notes in Computer Science
• Subjects: Combinational Circuit; Fault Injection; Fault Simulation; Sequential Circuit; Test Vector
• ISBN: 9783540240761; 3540240764
• ISSN: 0302-9743; 1611-3349
• DOI: 10.1007/978-3-540-30536-1_39

A Verilog HDL-based fault simulator for testing embedded cores-based synchronous sequential circuits is proposed in the paper to detect single stuck-line faults The simulator emulates a typical BIST (built-in self-testing) environment with test pattern generator that sends its outputs to a CUT (circuit under test) and the output streams from the CUT are fed into a response data analyzer. The fault simulator is suitable for testing sequential circuits described in Verilog HDL. The subject paper describes in detail the architecture and applications of the fault simulator along with the models of sequential elements used. Results on some simulation experiments on ISCAS 89 full-scan sequential benchmark circuits are also provided.