Design of a Low Power High Speed ALU in 45nm Using GDI Technique and Its Performance Comparison

• Published in: Computer Networks and Information Technologies pp. 458 - 463
• Main Authors: Kumar, Manish, Hussain, Md. Anwar, Singh, L. L. K.
• Format: Book Chapter
• Language: English
• Published: Berlin, Heidelberg Springer Berlin Heidelberg 2011
• Series: Communications in Computer and Information Science
• Subjects: CMOS; delay; GDI; power - delay product; power dissipation; PTL
• ISBN: 3642195415; 9783642195419
• ISSN: 1865-0929; 1865-0937
• DOI: 10.1007/978-3-642-19542-6_87

The paper presents a low power high speed Arithmetic Logic Unit (ALU) in 45 nm technology using Gate Diffusion Input (GDI) technique and its performance comparison with CMOS and nMOS Pass Transistor Logic (PTL) techniques. The simulated results revealed better performance characteristics of various logic and arithematic functions of a 1-bit ALU using GDI techniqueas compared to conventional CMOS and nMOS PTL techniques. GDI technique allows reducing power dissipation and delay while maintaining low complexity of logic design. MICROWIND and DSCH 3.1 EDA tools were used for the schematic layout and simulation of ALU using BSIM4 model.