Hardware Compilation Using SSA

• Published in: SSA-based Compiler Design pp. 329 - 345
• Main Authors: Diniz, Pedro C., Brisk, Philip
• Format: Book Chapter
• Language: English
• Published: Cham Springer International Publishing 2022
• Subjects: Code generation; Compiler back-end; Compiler design; Conditional move; Configuration logic blocks (CLBs); Control dependence; Data dependence; Datapath and control; Floor planning; FPGA; Functional language; gated SSA; Gating function; Hardware compilation; Hardware logic; High-level synthesis; If-conversion; Lookup table; Multiplexer; Program dependence graph (PDG); Referential transparency; Semi-partial representation of circuits; Spatial representation of circuits; Static single-assignment form (SSA form); Synchronous data flow; Temporal combination of circuits; VHDL
• ISBN: 303080514X; 9783030805142
• DOI: 10.1007/978-3-030-80515-9_23

This chapter describes the use of SSA-based high-level program representations for the realization of the corresponding computations using hardware digital circuits. We begin by highlighting the benefits of using a compiler SSA-based intermediate representation in this hardware mapping process, using an illustrative example. The subsequent sections describe hardware translation schemes for discrete hardware logic structures or datapaths of hardware circuits and outline several compiler transformations that benefit from SSA. We conclude with a brief survey of various hardware compilation efforts from both academia and industry that have adopted SSA-based internal representations.