Intel-22nm Squelch Yield Analysis and Optimization

It's always been a tough problem to make conservative estimate of yield due to limited silicon test samples. Besides, lack of understanding of relationship between yield and design parameters gives low confidence to designer. This paper gives rigorous mathematical treatment to the subject of yi...

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Bibliographic Details
Published inLecture notes in engineering and computer science Vol. 2; pp. 709 - 716
Main Author Shinde, Suhas Vishwasrao
Format Journal Article
LanguageEnglish
Published 01.01.2014
Subjects
Confidence
Design parameters
Estimates
Guidelines
Mathematical analysis
Optimization
Silicon
Online AccessGet full text
ISBN9789881925336
9881925339
ISSN2078-0958
2078-0966

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Summary:It's always been a tough problem to make conservative estimate of yield due to limited silicon test samples. Besides, lack of understanding of relationship between yield and design parameters gives low confidence to designer. This paper gives rigorous mathematical treatment to the subject of yield analysis and optimization. It outlines the approach for conservative estimate of yield even for smaller sample size, n < 25. It bridges the gap between our subjective knowledge to objective conclusions. Finally it analyses Intel-22nm USB2 Squelch circuit for yield and sets yield optimization guidelines.
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ISBN:9789881925336
9881925339
ISSN:2078-0958
2078-0966