A 100 x 100 pixel silicon retina for gradient extraction with steering filter capabilities and temporal output coding

• Published in: IEEE journal of solid-state circuits Vol. 37; no. 2; pp. 160 - 172
• Main Authors: Barbaro, Massimo, Burgi, Pierre-Yves, Mortara, Alessandro, Nussbaum, Pascal, Heitger, Friedrich
• Format: Journal Article
• Language: English
• Published: 01.02.2002
• ISSN: 0018-9200
• DOI: 10.1109/4.982422

A 100 x 100 pixel analog very large scale integration retina is proposed to extract the magnitude and direction of spatial gradients contained in sensed images. The retina implements in a massively parallel fashion, at pixel level, an algorithm based on the concept of steerable filters to compute the gradients. An output rate of up to 1000 frames per second is achieved in a standard CMOS 0.5 mu m process. The retina provides address-event coded output on two asynchronous buses, one dedicated to the the gradient's direction and another to the gradient's magnitude. The gradient information is temporally ordered from largest to smallest gradient's magnitude. Rationales for such an order are borrowed from information theory. Precise timing of the address events is controlled by a decreasing threshold function, whose slope can be dynamically modified to regulate the data flow on the communication bus so as to reduce the number of collisions. Quantitative experimental results from a fully functional silicon demonstrator are presented.