FPGA Implementation of RA-CORDIC Processor

In processing the real world data Digital Signal Processing algorithms provide unbeatable performance. One of the DSP algorithms is Coordinate Rotation Digital Computer (CORDIC). For real-time airborne computation, CORDIC actas a special purpose digital computer. Basically the CORDIC is categorized...

Full description

Saved in:
Bibliographic Details
Published inIndian journal of science and technology Vol. 6; no. 5; p. 4505
Main Authors Thirveedhi, Subha Sri, Rajappa, Muthaiah
Format Journal Article
LanguageEnglish
Published 01.05.2013
Subjects
Algorithms
Arithmetic
Digital computers
Digital signal processing
Field programmable gate arrays
Microprocessors
Synthesis
Online AccessGet full text
ISSN0974-6846

Cover

More Information
Summary:In processing the real world data Digital Signal Processing algorithms provide unbeatable performance. One of the DSP algorithms is Coordinate Rotation Digital Computer (CORDIC). For real-time airborne computation, CORDIC actas a special purpose digital computer. Basically the CORDIC is categorized in two different styles such as sequential (folded) and com- binational (unfolded). This paper presents a novel architecture of CORDIC using redundant arithmetic i.e., RA-CORDIC. The RA-CORDIC structure shows better latency and obtains maximum throughput. The structure has been coded in VERILOG, synthesis analysis are performed using Xilinx ISim tool and targeted on Xilinx FPGA synthesis tool.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0974-6846