A 1.248 Gb/s – 2.918 Gb/s Low-Power Receiver for MIPI-DigRF M-PHY with a Fast Settling Fully Digital Frequency Detection Loop in 0.11 μm CMOS

• Published in: Journal of semiconductor technology and science Vol. 15; no. 4; pp. 506 - 517
• Main Authors: Sang-Yun Kim, Juri Lee, Hyung-Gu Park, Young Gun Pu, Jae Yong Lee, Kang-Yoon Lee
• Format: Journal Article
• Language: English
• Published: 대한전자공학회 01.08.2015
• Subjects: 전기공학; fully digital frequency detection loop; low-power; fast phase tracking loop; clock and data recovery (CDR); MIPI-DigRF M-PHY; bandwidth switching
• ISSN: 1598-1657; 2233-4866
• DOI: 10.5573/JSTS.2015.15.4.506

This paper presents a 1.248 Gb/s – 2.918 Gb/s low-power receiver MIPI-DigRF M-PHY with a fully digital frequency detection loop. MIPI-DigRF M-PHY should be operated in a very short training time which is 0.01 μs the for HS-G2B mode. Because of this short SYNC pattern, clock and data recovery (CDR) should have extremely fast locking time. Thus, the quarter rate CDR with a fully digital frequency detection loop is proposed to implement a fast phase tracking loop. Also, a low power CDR architecture, deserializer and voltage controlled oscillator (VCO) are proposed to meet the low power requirement of MIPI-DigRF M-PHY. This chip is fabricated using a 0.11 μm CMOS process, and the die area is 600 μm x 250 μm. The power consumption of the receiver is 16 mW from the supply voltage of 1.1 V. The measured lock time of the CDR is less than 20 ns. The measured rms and peak jitter are 35.24 psp-p and 4.25 psrms respectively for HS-G2 mode. KCI Citation Count: 4