오정정 없이 온칩 메모리 보호를 위한 SEC-DED-DAEC 부호

As electronic devices technology scales down into the deep-submicron to achieve high-density, low power and high performance integrated circuits, multiple bit upsets by soft errors have become a major threat to on-chip memory systems. To address the soft error problem, single error correction, doubl...

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Bibliographic Details
Published in한국정보통신학회논문지 Vol. 26; no. 10; pp. 1559 - 1562
Main Author 전호윤(Hoyoon Jun)
Format Journal Article
LanguageKorean
Published 한국정보통신학회 2022
Subjects
Double Adjacent Error Correction
Soft Error
On-chip Memory
Error Correcting Code
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ISSN2234-4772
2288-4165

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Summary:As electronic devices technology scales down into the deep-submicron to achieve high-density, low power and high performance integrated circuits, multiple bit upsets by soft errors have become a major threat to on-chip memory systems. To address the soft error problem, single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) codes have been recently proposed. But these codes do not troubleshoot mis-correction problem. We propose the SEC-DED_DAEC code with without mis-correction. The decoder for proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the decoder can be employed on-chip memory system.
Bibliography:KISTI1.1003/JNL.JAKO202231159766532
ISSN:2234-4772
2288-4165