Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL

Verilog HDL is the most-used hardware design language for FPGAs. In this paper, we introduce Pyverilog, an open-source toolkit for RTL design analysis and code generation of Verilog HDL. Pyverilog offers efficient functionality to implement a CAD tool that treats Verilog HDL with small amount of eff...

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Bibliographic Details
Published inApplied Reconfigurable Computing Vol. 9040; pp. 451 - 460
Main Author Takamaeda-Yamazaki, Shinya
Format Book Chapter
LanguageEnglish
Published Switzerland Springer International Publishing AG 2015
Springer International Publishing
SeriesLecture Notes in Computer Science
Subjects
Algorithms & data structures
Analyzer
COMPUTER COMMUNICATIONS & NETWORKING
Computer hardware
FPGA
Parser
Toolkit
Verilog HDL
Online AccessGet full text
ISBN3319162136
9783319162133
ISSN0302-9743
1611-3349
DOI10.1007/978-3-319-16214-0_42

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Summary:Verilog HDL is the most-used hardware design language for FPGAs. In this paper, we introduce Pyverilog, an open-source toolkit for RTL design analysis and code generation of Verilog HDL. Pyverilog offers efficient functionality to implement a CAD tool that treats Verilog HDL with small amount of effort. Pyverilog consists of four key libraries: (1) parser, (2) dataflow analyzer, (3) control-flow analyzer, and (4) Verilog code generator. We show a case study that uses Pyverilog as the fundamental back-end library. We have developed flipSyrup, a framework for efficient rapid prototyping by virtually enlarging FPGA resources. By using Pyverilog, the framework is implemented with small amount of additional codes; it is implemented in about 2700 lines of code in Python.
ISBN:3319162136
9783319162133
ISSN:0302-9743
1611-3349
DOI:10.1007/978-3-319-16214-0_42