APA (7th ed.) Citation

Wang, Y., Pavlidis, V. F., Wang, R., & Cheng, Y. (2025). PV-Clock: Process Variation-Aware 3D Clock Network Synthesis for Robust and Power-Efficient Timing Optimization. Proceedings / IEEE Computer Society Annual Symposium on VLSI, 1, 1-6. https://doi.org/10.1109/ISVLSI65124.2025.11130256

Chicago Style (17th ed.) Citation

Wang, Yiyu, Vasilis F. Pavlidis, Rui Wang, and Yuanqing Cheng. "PV-Clock: Process Variation-Aware 3D Clock Network Synthesis for Robust and Power-Efficient Timing Optimization." Proceedings / IEEE Computer Society Annual Symposium on VLSI 1 (2025): 1-6. https://doi.org/10.1109/ISVLSI65124.2025.11130256.

MLA (9th ed.) Citation

Wang, Yiyu, et al. "PV-Clock: Process Variation-Aware 3D Clock Network Synthesis for Robust and Power-Efficient Timing Optimization." Proceedings / IEEE Computer Society Annual Symposium on VLSI, vol. 1, 2025, pp. 1-6, https://doi.org/10.1109/ISVLSI65124.2025.11130256.