PV-Clock: Process Variation-Aware 3D Clock Network Synthesis for Robust and Power-Efficient Timing Optimization

• Published in: Proceedings / IEEE Computer Society Annual Symposium on VLSI Vol. 1; pp. 1 - 6
• Main Authors: Wang, Yiyu, Pavlidis, Vasilis F., Wang, Rui, Cheng, Yuanqing
• Format: Conference Proceeding
• Language: English
• Published: IEEE 06.07.2025
• Subjects: 3D ICs; Clock Network Synthesis; Clocks; Geometric Optimization; Measurement; Multichip modules; Network synthesis; Optimization; Power demand; Process Variations; Robustness; Three-dimensional displays; Timing; Very large scale integration
• ISSN: 2159-3477
• DOI: 10.1109/ISVLSI65124.2025.11130256

Three-dimensional integration technology enables higher density and heterogeneous integration, extending Moore's Law. However, increasing integration density complicates clock network design. Existing synthesis methods often neglect process variations, which are inherent in fabrication and degrade clock signal precision. Additionally, optimizing one design metric, such as reducing clock skew, often increases power consumption, limiting overall efficiency. These trade-offs restrict the design space and hinder 3D IC performance. To address these challenges, this paper proposes a novel process variation-aware clock network synthesis technique incorporating a multi-objective collaborative optimization framework. The proposed method effectively balances clock skew and power consumption while enhancing robustness. Experimental results demonstrate significant improvements: clock skew is reduced from 21.54 p s to 15.02 p s, while clock power decreases by 23.8 \%, highlighting the method's effectiveness in mitigating process variations and optimizing 3D clock networks.