High-Performance FPGA-Based Accelerator of L-BFGS for 3D Face Reconstruction

• Published in: Proceedings / IEEE Computer Society Annual Symposium on VLSI Vol. 1; pp. 1 - 6
• Main Authors: Pan, Haoran, Xiong, Bohang, Tian, Jing, Zhang, Shikun, Zhu, Hao, Wang, Zhongfeng
• Format: Conference Proceeding
• Language: English
• Published: IEEE 06.07.2025
• Subjects: 3D face reconstruction; Approximation algorithms; Computational modeling; Computer architecture; Faces; Field programmable gate arrays; FPGA; hardware implementation; Image reconstruction; L-BFGS algorithm; Optimization; Solid modeling; Three-dimensional displays; Very large scale integration
• ISSN: 2159-3477
• DOI: 10.1109/ISVLSI65124.2025.11130257

D face reconstruction is a hot topic in computer graphics and vision, with many efficient algorithms recently proposed that offer good performance but suffer from high computational complexity. The FaceScape algorithm is promising, integrating prior knowledge to effectively recover highly detailed and riggable 3D face models from a single image input with high robustness. Its computations are relatively small but still cannot meet real-time requirements in most application scenarios. In this paper, we propose a high-speed hardware accelerator for the core part (namely the Limited-memory Broyden-Fletcher-Goldfarb-Shanno (L-BFGS) algorithm) of FaceScape aiming to deal with this problem. Many optimization techniques, especially novel algorithmic transformations and architectural schemes, have been introduced and applied. Experimental results demonstrate that our FPGA implementation of L-BFGS for FaceScape achieves approximately 5.6 \times speedup over the optimized C implementation and runs over 100 \times faster than the original Python implementation.