Parametric Optimization of Verilog-A code for Double-PHL of RRAM Device in a Step-by-Step Approach

• Published in: Devices for Integrated Circuit pp. 448 - 452
• Main Authors: Prajapati, Shivani, Tripathi, Priyanka, Dutta, Koushik
• Format: Conference Proceeding
• Language: English
• Published: IEEE 05.04.2025
• Subjects: Computer architecture; Data models; Hardware design languages; Hysteresis; Integrated circuit modeling; Interference; Memristor; Memristors; Multilevel Switching; Nonvolatile memory; Optimization; RRAM; Simmons Model; Threshold voltage
• ISSN: 2996-3044
• DOI: 10.1109/DevIC63749.2025.11012324

The requirement of precise mathematical modeling and corresponding Verilog-A implementation is pivotal for circuit designing of many applications, like, non-volatile memory, logic circuits, and neuromorphic computing, with memristor devices, possessing pinched hysteresis loop (PHL) in I-V characteristics. A few works were reported with single PHL behavior; but yet to correlate with multilevel PHL, as aligned with experimental reports. The present work focuses on the development of such a model by optimization in the parametric level in the Simmons model, well adopted to describe single PHL conventionally, step-by-step, alteration of parameters and comparison with experimental data is the key methodology of this work. Proposing threshold voltage, as a new parameter, is substantial for appreciable agreement for simultaneous matching of the double loop (PHL) case. The matching shows an appreciable error of ~7% for lower-voltage PHL and that of ~3% for higher-voltage PHL.