Performance Analysis of Fast Fourier Transforms Using Binary Signed Digit Number System

It is a very efficient way to implement the Fast Fourier Transform (FFT) and is in use for various applications, such as radar communication, biomedical signal processing, and multicarrier modulation systems. A butterfly step can be implemented as a repetitive multiplier followed by an adder of comp...

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Bibliographic Details
Published in2024 International Conference on Power, Energy, Control and Transmission Systems (ICPECTS) pp. 1 - 4
Main Authors Joy Kinol, A. Mary, R M, Bommi, G, Uganya, Nalini, M.
Format Conference Proceeding
LanguageEnglish
Published IEEE 08.10.2024
Subjects
Adders
Arithmetic
Binary signed Digit Representation
Fast Fourier Transform
Fast Fourier transforms
Floating point Butterfly Unit
Performance evaluation
Power demand
Power dissipation
Radar applications
Radar signal processing
Signal processing algorithms
Throughput
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DOI10.1109/ICPECTS62210.2024.10780027

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Summary:It is a very efficient way to implement the Fast Fourier Transform (FFT) and is in use for various applications, such as radar communication, biomedical signal processing, and multicarrier modulation systems. A butterfly step can be implemented as a repetitive multiplier followed by an adder of complex numbers. The current work has made an enormous effort to improve the speed and computational complexity of arithmetic operations occurring inside the butterfly unit by a detailed investigation of different adders and multipliers. A new method to design adder and multiplier for the computation of butterfly is proposed, in which the carry propagation is directed out effectively through a format Binary Signed Digit (BSD). When such two unit results were compared, it was found that the BSD based floating-point butterfly performs much better, giving considerable gains in processing speed and efficiency.
DOI:10.1109/ICPECTS62210.2024.10780027