A graph-based algorithm for NVM address decoders testing

Test coverage and test cost are of primary importance in the production process of microcontrollers for automotive applications. Non-volatile memories play a major role in this respect, and a lot of effort was spent in the past to define strategies for reaching zero-defects targets. This paper intro...

Full description

Saved in:
Bibliographic Details
Published inProceedings - International Test Conference pp. 417 - 425
Main Authors Scaramuzza, Pierre, Kern, Thomas, Coppetta, Matteo, Grossi, Alessandro, Ullmann, Rudolf
Format Conference Proceeding
LanguageEnglish
Published IEEE 03.11.2024
Subjects
decoder
Decoding
graph
memory
Memory management
Microcontrollers
Nonvolatile memory
Observability
Production
RRAM
Software
Software algorithms
Technological innovation
test
Testing
Online AccessGet full text
ISSN2378-2250
DOI10.1109/ITC51657.2024.00064

Cover

More Information
Summary:Test coverage and test cost are of primary importance in the production process of microcontrollers for automotive applications. Non-volatile memories play a major role in this respect, and a lot of effort was spent in the past to define strategies for reaching zero-defects targets. This paper introduces a solution for screening defective memory address decoders, with a special focus on RRAM modules architectures. The strength of the proposed approach relies on the definition of a decoder graph model and on an optimal algorithm to traverse it. The presented software-based test, executed on high volumes of several microcontrollers families, decreases field application returns and ensures a consistent test time reduction with respect to the previous implementation.
ISSN:2378-2250
DOI:10.1109/ITC51657.2024.00064