Area-Efficient FPGA Implementations of the SHA-3 Finalists

• Published in: 2011 International Conference on Reconfigurable Computing and FPGAs pp. 235 - 241
• Main Authors: Jungk, B., Apfelbeck, J.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.11.2011
• Subjects: Adders; Clocks; Compact Implementation; Computer architecture; Cryptography; Field programmable gate arrays; FPGA; Hash Functions; Pipeline processing; Random access memory; SHA-3; Throughput
• ISBN: 9781457717345; 1457717344
• ISSN: 2325-6532
• DOI: 10.1109/ReConFig.2011.16

Secure cryptographic hash functions are core components in many applications like challenge-response authentication systems or digital signature schemes. Many of these applications are used in cost-sensitive markets and thus slow budget implementations of such components are very important. In the present paper, we focus on the new SHA-3 competition, started by the National Institute of Standards and Technology (NIST), which searches for a new hash function in response to security concerns regarding the previous hash functions SHA-1 and the SHA-2 family. This work adds new valuable data to the competition, by providing an evaluation of area-efficient implementations of all finalists. Our results show, that it is possible to implement all candidates reasonably small. We focus on area-efficiency and therefore we do not rank the candidates by absolute throughput, but rather by the area and the throughput-area ratio. The results hint that Grøstl and Keccak are the best overall performers for compact implementations, if the throughput-area ratio is most important. The following candidate is BLAKE, while the Skein and JH implementations trail behind. The area ranking changes the results and puts JH on the top, followed by BLAKE, Grøstl, Keccak and Skein.