A C-based algorithm development flow for a reconfigurable processor architecture

• Published in: 2003 International Symposium on System-on-Chip pp. 69 - 73
• Main Authors: Mucci, C., Chiesa, C., Lodi, A., Toma, M., Campi, F.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2003
• Subjects: Algorithm design and analysis; Design optimization; Digital signal processing; Embedded system; Energy consumption; Hardware; High level languages; Reduced instruction set computing; Signal processing algorithms; VLIW
• ISBN: 0780381602; 9780780381605
• DOI: 10.1109/ISSOC.2003.1267720

Reconfigurable processors are an appealing option to achieve high performance and low energy consumption in digital signal processing, but their utilization often involves hardware issues not usual for algorithm developers proficient in high level languages. This paper presents a C-based algorithm development flow for XiRisc, a reconfigurable processor architecture targeted at embedded systems, that couples a VLIW risc core with a custom designed programmable hardware unit optimized for being programmed starting from data flow graph (DFG) descriptions. Starting from C-language, the flow produces both executable codes for the processor core and configuration bits for the embedded programmable unit. The proposed flow was utilized for implementing a set of DSP algorithms on a prototypal 0.18 /spl mu/m XiRisc test-chip obtaining performance speed-ups up to 10x and energy consumption reduction up to 75%.