Analysis and Parallelization of H.264 decoder on Cell Broadband Engine Architecture

• Published in: 2007 IEEE International Symposium on Signal Processing and Information Technology pp. 791 - 795
• Main Authors: Hyunki Baik, Kue-Hwan Sihn, Yun-il Kim, Sehyun Bae, Najeong Han, Hyo Jung Song
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2007
• Subjects: Automatic voltage control; Bit rate; Cell Broadband Engine Processor; Computational efficiency; Computer architecture; Data Partitioning; Decoding; Engines; Functional Partitioning; H.264; Multicore; Multicore processing; Parallel Processing; Process design; SIMD; Video coding; Video compression
• ISBN: 9781424418343; 1424418348
• ISSN: 2162-7843
• DOI: 10.1109/ISSPIT.2007.4458128

Emerging video coding technology like H.264/AVC achieves high compression efficiency, which enables high quality video at the same or lower bitrate. However, those advanced coding techniques come at the cost of more computational power. Developed with such multimedia applications in mind, the CELL broadband engine (BE) processor was designed as a heterogeneous on-chip multicore processor to meet the required high performance. In this paper, we analyze the computational requirements of H.264 decoder per-module basis and implement parallelized H.264 decoder on the CELL processor based on the profile result. We propose and implement a hybrid partitioning technique that combines both functional and data partitioning to avoid the dependencies imposed by H.264 decoder, and optimize it using SIMD instructions. Through experiments, the parallelized H.264 decoder runs about 3.5 times faster than the single core (PPE only) decoder, by using 1 PPE and 4 SPEs.