24.5 A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning

• Published in: Digest of technical papers - IEEE International Solid-State Circuits Conference pp. 396 - 398
• Main Authors: Si, Xin, Chen, Jia-Jing, Tu, Yung-Ning, Huang, Wei-Hsing, Wang, Jing-Hong, Chiu, Yen-Cheng, Wei, Wei-Chen, Wu, Ssu-Yen, Sun, Xiaoyu, Liu, Rui, Yu, Shimeng, Liu, Ren-Shuo, Hsieh, Chih-Cheng, Tang, Kea-Tiong, Li, Qiang, Chang, Meng-Fan
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2019
• Subjects: Bandwidth; Common Information Model (computing); Machine learning; SRAM cells; Transistors
• ISSN: 2376-8606
• DOI: 10.1109/ISSCC.2019.8662392

Computation-in-memory (CIM) is a promising avenue to improve the energy efficiency of multiply-and-accumulate (MAC) operations in AI chips. Multi-bit CNNs are required for high-inference accuracy in many applications [1-5]. There are challenges and tradeoffs for SRAM-based CIM: (1) tradeoffs between signal margin, cell stability and area overhead; (2) the high-weighted bit process variation dominates the end-result error rate; (3) trade-off between input bandwidth, speed and area. Previous SRAM CIM macros were limited to binary MAC operations for fully connected networks [1], or they used CIM for multiplication [2] or weight-combination operations [3] with additional large-area near-memory computing (NMC) logic for summation or MAC operations.