FPGA implementation of binary coded decimal digit adders and multipliers

• Published in: 2012 8th International Symposium on Mechatronics and its Applications pp. 1 - 5
• Main Authors: Al-Khaleel, O. D., Tulic, N. H., Mhaidat, K. M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.04.2012
• Subjects: Adders; Delay; Design automation; Encoding; Field programmable gate arrays; Hardware; Table lookup
• ISBN: 9781467308601; 1467308609
• DOI: 10.1109/ISMA.2012.6215199

Decimal arithmetic has gained high impact on the overall performance of today's financial and commercial applications. Decimal additions and multiplication are the main decimal operations used in any decimal arithmetic algorithm. Decimal digit adders and decimal digit multipliers are usually the building blocks for higher order decimal adders and multipliers. FPGAs provide an efficient hardware platform that can be employed for accelerating decimal algorithms. In this paper, different designs for two decimal digit adders and one decimal digit multiplier are proposed. The proposed designs were described, functionally tested, and implemented using VHDL and the Xilinx ISE 10.1 targeting Xilinx Vertix-5 XC5VLX30-3 FPGA. Implementation results and comparison with existing designs are provided.