On the design, control, and use of a reconfigurable heterogeneous multi-core system-on-a-chip

• Published in: 2008 IEEE International Symposium on Parallel and Distributed Processing pp. 1 - 11
• Main Authors: Kwok, T.T.-O., Yu-Kwong Kwok
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.04.2008
• Subjects: Batteries; Concurrent computing; Control systems; Design engineering; Embedded system; Energy efficiency; Field programmable gate arrays; FPGA; heterogeneous multi-core; network-on-chip (NoC); Parallel processing; reconfigurable computing; System-on-a-chip; system-on-a-chip (SoC); Very large scale integration
• ISBN: 1424416930; 9781424416936
• ISSN: 1530-2075
• DOI: 10.1109/IPDPS.2008.4536165

With the continued progress in VLSI technologies, we can integrate numerous cores in a single billion-transistor chip to build a multi-core system-on-a-chip (SoC). This also brings great challenges to traditional parallel programming as to how we can increase the performance of applications with increased number of cores. In this paper, we meet the challenges using a novel approach. Specifically, we propose a reconfigurable heterogeneous multi-core system. Under our proposed system, in addition to conventional processor cores, we introduce dynamically reconfigurable accelerator cores to boost the performance of applications. We have built a prototype of the system using FPGAs. Experimental evaluation demonstrates significant system efficiency of the proposed heterogeneous multi-core system in terms of computation and power consumption.