Run-Time Computation and Communication Aware Mapping Heuristic for NoC-Based Heterogeneous MPSoC Platforms

• Published in: 2011 Fourth International Symposium on Parallel Architectures, Algorithms and Programming pp. 203 - 207
• Main Authors: Kaushik, Samarth, Singh, Amit Kumar, Jigang, Wu, Srikanthan, Thambipillai
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2011
• Subjects: Algorithm design and analysis; Computer architecture; Hardware; Heterogeneous architectures; Heuristic algorithms; mapping heuristics; MPSoC design; Network-on-Chip (NoC); Program processors; Software algorithms
• ISBN: 1457718081; 9781457718083
• ISSN: 2168-3034
• DOI: 10.1109/PAAP.2011.32

The rapid increase in the complexity of real-life applications has led to the perpetual demand of refined architectural designs. Multiprocessor systems-on-chip (MPSoC) emerges as one of the possible solution for satiating such enormous computational needs. These MPSoCs are employed with Network-On-Chip (NoC) interconnect for power efficient and scalable inter-communication required between processors. Mapping parallelized tasks of applications onto these MPSoCs is the next gigantic problem, which can be done either at design-time or at run-time. However, design-time strategies may sometimes provide a more optimal mapping but they are restricted to predefined set of applications and seem incapable of run-time resource management. On the contrary, run-time mapping techniques overcome this limitation by determining the state of the platform and incorporating resource management before mapping. This paper describes a heuristic for run-time mapping of parallelized tasks of an application considering efficient computation, communication and resource utilization as the main parameters for optimization.