APA (7th ed.) Citation

Onizawa, N., Ikeda, T., Hanyu, T., & Gaudet, V. (2007, August). 3.2-Gb/s 1024-b rate-1/2 LDPC decoder chip using a flooding-type update-schedule algorithm. 2007 50th Midwest Symposium on Circuits and Systems, 217-220. https://doi.org/10.1109/MWSCAS.2007.4488574

Chicago Style (17th ed.) Citation

Onizawa, N., T. Ikeda, T. Hanyu, and V.C Gaudet. "3.2-Gb/s 1024-b Rate-1/2 LDPC Decoder Chip Using a Flooding-type Update-schedule Algorithm." 2007 50th Midwest Symposium on Circuits and Systems Aug. 2007: 217-220. https://doi.org/10.1109/MWSCAS.2007.4488574.

MLA (9th ed.) Citation

Onizawa, N., et al. "3.2-Gb/s 1024-b Rate-1/2 LDPC Decoder Chip Using a Flooding-type Update-schedule Algorithm." 2007 50th Midwest Symposium on Circuits and Systems, Aug. 2007, pp. 217-220, https://doi.org/10.1109/MWSCAS.2007.4488574.