3.2-Gb/s 1024-b rate-1/2 LDPC decoder chip using a flooding-type update-schedule algorithm

• Published in: 2007 50th Midwest Symposium on Circuits and Systems pp. 217 - 220
• Main Authors: Onizawa, N., Ikeda, T., Hanyu, T., Gaudet, V.C.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.08.2007
• Subjects: Bit error rate; Clocks; CMOS technology; Computer architecture; Frequency; Integrated circuit interconnections; Iterative decoding; Parity check codes; Throughput; Wiring
• ISBN: 1424411750; 9781424411757
• ISSN: 1548-3746
• DOI: 10.1109/MWSCAS.2007.4488574

This paper presents a high-speed low-density parity-check (LDPC) decoder chip using a new decoding algorithm, called a flooding-type update-schedule algorithm. Since node computations are performed using partially updated messages in the proposed algorithm, because of the good similarity among time-consecutive messages, data-transmission bottleneck between nodes for node computation is greatly reduced. Moreover, longer wires between nodes are appropriately divided into several subwires by inserting flip-flops so that system clock frequency for the LDPC decoding scheme can be much increased while maintaining the same BER as a conventional algorithm using fully updated messages. In fact, a throughput of 3.2 Gb/s in a 1024-b LDPC decoder chip under 90 nm CMOS technology is attained with the sufficient BER.