A novel floating point comparator using parallel tree structure

• Published in: 2015 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2015] pp. 1 - 6
• Main Authors: Samuel, Anuja T., Senthilkumar, Jawahar
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.03.2015
• Subjects: Clocks; Computer architecture; Computers; Delays; Floating point number; IEEE 754 format; Logic gates; Microprocessors; parallel prefix tree
• DOI: 10.1109/ICCPCT.2015.7159395

In recent years, floating point numbers are widely adopted due to its good robustness against quantization errors and high dynamic range capabilities. In this paper, a novel single-precision floating point comparator design is proposed. A parallel prefix tree structure is literally the back bone of this comparator design. This is designed using Verilog code, simulated and synthesised using CADENCE ENCOUNTER tool with TSMC 180nm technology. The proposed comparator fully supports single precision floating-point comparisons, as defined in the IEEE 754 standard. The proposed floating point comparator design exploits the advantages of structural reusability. Cadence Encounter synthesis for a 32-b floating point comparator shows a worst case input-output delay of 3.014 ns and a total power dissipation of 91.8μW using 0.18-μm TSMC technology. The replacement of NOR-NAND gate using OR gate in the decision module incurs the improvement in the performance which thereby outperforms the existing design.