Fixed-point FPGA model-based design and optimization for Henon map chaotic generator

• Published in: IEEE ... Latin American Symposium on Circuits and Systems (Online) pp. 1 - 4
• Main Author: Lei Zhang
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2017
• Subjects: Chaotic communication; Clocks; Field programmable gate arrays; Generators; Hardware; Mathematical model; Registers
• ISSN: 2473-4667
• DOI: 10.1109/LASCAS.2017.7948065

Chaotic systems can be used for secure communication such as transmitting video, audio and text files. Various chaotic generators have been implemented on FPGA in realtime for synchronous communication applications. In this paper, a detailed design approach is presented to implement modelbased chaotic generator designs on FPGA. Henon map has its significance in studying chaotic systems and is used as the design subject in this paper. The conceptual model design is built using MATLAB Simulink, and the equivalent model is created for FPGA implementation using Xilinx System Generator. 32-bit floating point, 32-bit fixed-point and 16-bit fixed-point design models are implemented on FPGA separately to evaluate the design performance, i.e. the maximum operating clock frequency (performance) and resource utilization. The 16-bit fixed-point model is further optimized for FPGA implementation to increase the frequency. A Xilinx Zedboard is used for hardware implementation. The implementation results show that the new design approach achieves promising improvement on design performance by increasing the maximum operating frequency from below 15.3 MHz to more than 105.29 MHz, and meanwhile reducing FPGA resource usage by approximately 75%. The FPGA hardware co-simulation results demonstrate that the optimized 16-bit fixed point model can successfully generate the Henon map chaotic outputs, compared to the MATLAB simulation results with double precision. The optimized design can achieve increased data throughput at the cost of increased hardware resource utilization by adding pipelining.