A 65nm 1Gb 2b/Cell NOR Flash with 2.25MB/s Program Throughput and 400MB/s DDR interface

A 1.8V 1 Gb 2b/cell NOR flash memory is based on a time-domain voltage-ramp reading concept and designed in a 65nm technology. The program method, architecture and algorithm to reach 2.25MB/S programming throughput are presented. The read concept allows 70ns random access time and a 400MB/S sustaine...

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Published in2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers pp. 476 - 616
Main Authors Villa, Corrado, Vimercati, Daniele, Schippers, Stefan, Polizzi, Salvatore, Scavuzzo, Andrea, Perroni, Maurizio, Gaibotti, Maurizio, Sali, Mauro Luigi
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.02.2007
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ISBN1424408520
9781424408528
ISSN0193-6530
DOI10.1109/ISSCC.2007.373501

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Summary:A 1.8V 1 Gb 2b/cell NOR flash memory is based on a time-domain voltage-ramp reading concept and designed in a 65nm technology. The program method, architecture and algorithm to reach 2.25MB/S programming throughput are presented. The read concept allows 70ns random access time and a 400MB/S sustained read throughput via a DDR interface
ISBN:1424408520
9781424408528
ISSN:0193-6530
DOI:10.1109/ISSCC.2007.373501